Setting clock & PLL

I'd like to slow down my Stamp9G20 clock. I know it is something tricky to do in Linux, but can I do that in U-Boot? How can I manage the DBG interface frequency to stay connected?

Re: Setting clock & PLL

When manipulation the system clock in U-Boot, you also have to adjust the "Debug Unit Baud Rate Generator Register" (DBGU_BRGR). It simply contains a divider that is applied to MCK/16 if greater than 1. See 28.5.9 of the AT91SAM9G20 technical manual available at atmel.com.

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