16. DMA Controller (DMAC)

The DMA Controller (DMAC) supports the following transfer schemes:

  • Peripheral-to-Memory

  • Memory-to-Peripheral

  • Peripheral-to-Peripheral

  • Memory-to-Memory

The DMAC contains unidirectional and bidirectional channels. The full-duplex peripherals feature unidirectional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature one bidirectional channel. Typically full-duplex peripherals are USARTs, SPI or SSC. The HSMCI is a half duplex device.

The SAMA5 microcontrollers have two DMA controllers connected to the AMBA peripheral bridge. DMAC0 handles transfers between peripherals and memory from peripherals connected on APB0 ( AMBA Peripheral Bridge 0).

Instance T/R Channel Interface Number
HSMCI0 Receive/Transmit0
SPI0 Transmit 1
SPI0 Receive 2
USART0 Transmit 3
USART0 Receive 4
USART1 Transmit 5
USART1 Receive 6
TWI0 Transmit 7
TWI0 Receive 8
TWI1 Transmit 9
TWI1 Receive 10
UART0 Transmit 11
UART0 Receive 12
SSC0 Transmit 13
SSC0 Receive 14
SMD Transmit 15
SMD Receive 16

Table 5.4. DMAC0 Channels Definition


DMAC1 handles transfers between peripherals and memory from peripherals connected on APB1 ( AMBA Peripheral Bridge 1).

Instance T/R Channel Interface Number
HSMCI1 Receive/Transmit0
HSMCI0 Receive/Transmit1
ADC Receive 2
SSC1 Transmit 3
SSC1 Receive 4
UART1 Transmit 5
UART1 Receive 6
USART2 Transmit 7
USART2 Receive 8
USART3 Transmit 9
USART3 Receive 10
TWI2 Transmit 11
TWI2 Receive 12
DBGU Transmit 13
DBGU Receive 14
SPI1 Transmit 15
SPI1 Receive 16
SHA Transmit 17
AES Transmit 18
AES Receive 19
TDES Transmit 20
TDES Receive 21

Table 5.5. DMAC1 Channels Definition


Using the DMAC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. The DMAC supports single transfer and chained buffer transfer. In chained buffer transfer mode, the address is automatically incremented, when the countable limit of the current transfer buffer is reached.

To launch a transfer, the peripheral triggers its associated DMA channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself. There are four kinds of interrupts generated by the DMAC:

  • Buffer Transfer Completed

  • Chained Buffer Transfer Completed

  • Access Error

  • Descriptor Integrity Check Error