4. Bus Matrix

The bus matrix of AT91SAM-controllers allows many master and slave devices to be connected independently of each other. Each master has a decoder and can be defined specially for each master. This allows concurrent access of masters to their slaves (provided the slave is available).

The bus matrix is thus the bridge between external devices connected to the EBI, the microcontroller's embedded peripherals and the CPU core.

Master 0 Cortex A5
Master 1 DMA Controller 0
Master 2 DMA Controller 0
Master 3 DMA Controller 0
Master 4 DMA Controller 1
Master 5 DMA Controller 1
Master 6 DMA Controller 1
Master 7 Gigabit Ethernet MAC DMA
Master 8 LCD DMA
Master 9 LCD DMA
Master 10 USB Host High Speed EHCI DMA
Master 11 USB HOST OHCI DMA
Master 12 USB Device High Speed DMA
Master 13 Ethernet MAC DMA
Master 14 ISI Controller DMA

Table 5.1. Bus Matrix Masters


Slave 0 Internal SRAM 0
Slave 1 Internal SRAM 1
Slave 2 NFC SRAM
Slave 3 Internal ROM
Slave 4 Soft Modem (SMD)
Slave 5UDP High Speed Dual RAM
USB OHCI
USB EHCI
Slave 6 External Bus Interface
Slave 7 DDR2 Port 0
Slave 8 DDR2 Port 1
Slave 9 DDR2 Port 2
Slave 10 DDR2 Port 3
Slave 11 Peripheral Bridge 0
Slave 12 Peripheral Bridge 1

Table 5.2. Bus Matrix Slaves