4. Bus Matrix

The bus matrix of AT91SAM-controllers allows many master and slave devices to be connected independently of each other. Each master has a decoder and can be defined specially for each master. This allows concurrent access of masters to their slaves (provided the slave is available).

The bus matrix is thus the bridge between external devices connected to the EBI, the microcontroller's embedded peripherals and the CPU core.

Master 0 ARM926™ Instruction
Master 1 ARM926™ Data
Master 2 PDC
Master 3 USB HOST OHCI
Master 4 DMA
Master 5 DMA
Master 6 ISI Controller DMA
Master 7 LCD DMA
Master 8 Ethernet MAC DMA
Master 9 USB Device High Speed DMA
Master 10 USB Host High Speed EHCI DMA
Master 11 Reserved

Table 4.1. Bus Matrix Masters


Slave 0 Internal SRAM
Slave 1Internal ROM
USB OHCI
USB EHCI
UDP High Speed RAM
LCD User Interface
Reserved
Slave 2 DDR Port 0
Slave 3 DDR Port 1
Slave 4 DDR Port 2
Slave 5 DDR Port 3
Slave 6 External Bus Interface
Slave 7 Internal Peripherals

Table 4.2. Bus Matrix Slaves