Appendix D. PortuxG20 Pin Assignment

Processor Pin Peripheral A Peripheral B
1 PB31 PCK1 ISI_MCK
2 PB13 RXD5 ISI_D11
3 PB03 SPI1_NPCS0 TIOA5
4 PB01 SPI1_MOSI TIOB3
5 GND
6 PA07 MCCDA
7 PA09 MCDA1
8 PA11 MCDA3 ETX3
9 PB21 RF0 ISI_D1
10 PA30 SCK2 RXD4
11 PA03 SPI0_NPCS0 MCDB3
12 PA01 SPI0_MOSI MCCDB
13 GND
14 BPC05 SPI1_NPCS1 A24
15 PB11 RXD3 ISI_D09
16 BPC10 CTS3 A25
17 BPC06 CFCE1 TIOB2
18 BPC04 SPI1_NPCS2 A23
19 HDPB
20 PB17 TF0 TCLK4
21 PB07 RXD1 TCLK2
22 PB19 RD0 TIOB5
23 PB29 CTS1 ISI_VSYNC
24 GND
25 PC01 PCK0 AD1
26 PC03 SPI1_NPCS3 AD3
27 PA23 TWD ETX2
28 PB22 DSR0 ISI_D2
29 PB05 RXD0
30 PB24 DTR0 ISI_D4
31 PB27 CTS0 ISI_D7
32 GND

Table D.1. Pin Assignment PXB Row A


Processor Pin Peripheral A Peripheral B
1 VCC3.3
2 PB30 PCK0 ISI_HSYNC
3 PB12 TXD5 ISI_D10
4 PB02 SPI1_SPCK TIOA4
5 PB00 SPI1_MISO TIOA3
6 PA06 MCCDA0
7 PA08 MCCK
8 PA10 MCDA2 ETX2
9 VCC3.3
10 PB20 RK0 ISID0
11 PA31 SCK0 TXD4
12 PA02 SPI0_SPCK
13 PA00 SPI0_MISO MCCDB0
14 VBAT
15 VCC5.0
16 PB10 TXD3 ISI_D8
17 BPC08 BNCS4 BRTS3
18 NRST
19 HDMB
20 VCC3.3
21 PB16 TK0 TCLK3
22 PB06 TXD1 TCLK1
23 PB28 RTS1 ISI_PCK
24 PB18 TD0 TIOB4
25 PC00 SCK1 AD0
26 PC02 PCK1 AD2
27 PA24 TWCK ETX3
28 VCC3.3
29 PB25 RI0 ISI_D5
30 PB04 TXD0
31 PB26 RTS0 ISI_D6
32 PB23 DCD0 ISI_D3

Table D.2. Pin Assignment PXB Row B


Processor Pin Peripheral A Peripheral B
1BD00
2BD01
3BD02
4BD03
5BD04
6BD05
7BD06
8BD07
9BD08
10BD09
11BD10
12BD11
13BD12
14BD13
15BD14
16BD15
17 BNRD BCFOE
18 BNWR0 BCFWE BNWE
19BNWR1 BNBS1 BCFIOR
20 BPC15 BIRQ1 BNWAIT
21 BNCS0
22 BPC11 BNCS2 BSPI0_NPCS1
23BA00 BNBS0
24BA01 BNBS2 BNWR2
25BA02
26BA03
27BA04
28BA05
29BA06
30BA07
31BA08
32BA09

Table D.3. Pin Assignment PXB Row C