Appendix C. Address Map (Physical Address Space)

After the execution of the remap command the 4 GB physical address space is separated as shown in the following table. Accessing these addresses directly is only possible if the MMU (memory management unit) is deactivated. As soon as the MMU is activated the visible address space is changed completely. If absolute memory addresses should be accessed within an application, the corresponding address space has first to be mapped to the virtual address space using mmap or ioremap under Linux.

Address (Hex)Mnemonic Function
00 0000 Boot Memory NCS0 or internal ROM or internal SRAM (depending on BMS and REMAP)
10 0000 ROM Internal ROM 32 kByte
20 0000 SRAM0 Internal SRAM 16 kByte
30 0000 SRAM1 Internal SRAM 16 kByte
50 0000 UHP USB Host Port
1000 0000 EBI NCS0 Chip Select 0
2000 0000 EBI NCS1 Chip Select 1: SDRAM
3000 0000 EBI NCS2 Chip Select 2
4000 0000 EBI NCS3 Chip Select 3: NAND
5000 0000 EBI NCS4 Chip Select 4
6000 0000 EBI NCS5 Chip Select 5
7000 0000 EBI NCS6 Chip Select 6
8000 0000 EBI NCS7 Chip Select 7
FFFA 0000 TC0, TC1, TC23 Timer Counter, 16-Bit
FFFA 4000 UDP USB Device Port
FFFA 8000 MCI Multimedia Card / SD-Card Interface
FFFA C000 TWI Two Wire Interface (I²C)
FFFB 0000 USART0 Synchronous or Asynchronous Serial Port #0
FFFB 4000 USART1 Synchronous or Asynchronous Serial Port #1
FFFB 8000 USART2 Synchronous or Asynchronous Serial Port #2
FFFB C000 SSC Serial Synchronous Controller (I²S)
FFFC 0000 ISI Image Sensor Interface
FFFC 4000 EMAC Ethernet Controller
FFFC 8000 SPI0 Serial Peripheral Interface #0
FFFC C000 SPI1 Serial Peripheral Interface #1
FFFD 0000 USART3 Synchronous or Asynchronous Serial Port #3
FFFD 4000 USART4 Synchronous or Asynchronous Serial Port #4
FFFD 8000 USART5 Synchronous or Asynchronous Serial Port #5
FFFD C000 TC3, TC4, TC53 Timer Counter, 16-Bit
FFFE 0000 ADC Analog Digital Converter
FFFF E800 ECC Error Correction Controller
FFFF EC00 SMC Static Memory Controller
FFFF EE00 MATRIX Bus Matrix User Interface
FFFF F000 AIC Advanced Interrupt Controller
FFFF F200 DBGU Debug Unit, including UART
FFFF F400 PIOA 32 Bit Parallel I/O Controller A
FFFF F600 PIOB 32 Bit Parallel I/O Controller B
FFFF F800 PIOC 32 Bit Parallel I/O Controller C
FFFF FC00 PMC Power Management Controller
FFFF FD00 RSTC Reset Controller, Battery Powered
FFFF FD10 SHDWC Shutdown Controller, Battery Powered
FFFF FD20 RTT Real-time Timer 32 Bit, Battery Powered
FFFF FD30 PIT Periodic Interval Timer 32 Bit
FFFF FD40 WDT Watchdog Timer
FFFF FD50 GPBR 4 General Purpose Backup Registers

Table C.1. Physical Address Space