26. LCD controller

The LCD controller of the AT91SAM9261 (theoretically) supports displays with a resolution of up to 2048x2048 with a color depth of up 24 bits per pixel.

The LCD controller relies on a relatively simple frame buffer concept, which means that all graphics and character functions have to be implemented in software: character sets and graphic primitives are not integrated in the controller.

26.1. LCDC Initialisation and LCD Power Sequencing

LCD cells (pixels) should not be subjected to DC power for prolonged periods of time, as chemical decomposition might take place. The LCD controller therefore provides for a strict AC control of the LCD pixels. To do so, the LCD controller has to be initialized appropriately. Switching on the LCD supply voltage therefore has to take place after the LCDC initialization or shortly before.

Accordingly, the LCDC should not be powered down without deactivating the LCD supply voltage. The same is true if the LCDC is stopped indirectly by stopping the respective clock source, namely the PLLA.

The LCD backlight supply is not involved in these considerations. It may switched on or off at any time independently of the state of the LCDC.

26.2. LCDC Video Memory Selection

The video memory of the LCDC is part of the working memory of the processor. It might either reside in the internal SRAM, as well as in the external SDRAM. Using the internal SRAM has the advantage that the LCDC can access its video memory via an autonomous bus and does not affect the processor performance. However, as the internal SRAM has a capacity of only 160 kBytes, the color depth for a QVGA display is only 16 bit / pixel (320 x 240 x 2 = 153600 bytes are necessary). For a high quality display 16 bit per pixel might not be sufficient.

On the other hand, using the SDRAM as video memory has the advantage that there is plenty of space for all resolutions. Also the internal SRAM is now available for time critical software sections. Of course the LCDC will now be permanently scanning its video memory and might therefore reduce the overall performance to some degree.

26.3. LCDC Frame Buffer

The LCDC video memory is organized as a frame buffer in a straight forward way. It supports color depths of 1, 2, 4, 8, 16, or 24 bit per pixel. The video data is stored in a packed form with no unused bits in the video memory.

The color resolutions of 1, 2, 4, and 8 bpp (bits per pixel) use a palette table which is made up of 16-bit entries. The value of each pixel in the frame buffer serves as an index into the palette table. The value of the respective palette table entry is output to the display by the LCDC, see Table 4.4, “LCDC palette entry”.


Table 4.4. LCDC palette entry

The bits 2..0 of each color channel are not used in the palettized configuration — they are set to 0. The intensity bit sets the least significant valid bits of every color, that is, the bits 2, 10, and 18 of a 24-bit LCDC output word.

The same scheme as above is used in the 16-bit color resolution configuration, although in this case the frame buffer entry is output directly to the display instead of indexing a palette table.

In the 24-bit color resolution configuration, each frame buffer entry consists of one byte for each color, see Table 4.5, “LCDC 24 bit memory organization”.


Table 4.5. LCDC 24 bit memory organization

The "BGR" (blue-green-red) sequence in the AT91SAM9261 LCDC is not frequently used by graphics libraries or bitmaps ("RGB" is more of a standard), neither is the use of bit 15 as an intensity bit. Of course, the first problem can be circumvented by connecting the LCDC lines to the LCD in a way deviating from the Atmel designation, that is, by exchanging the "blue" against the "red" lines.

The Linux frame buffer driver offers a function which returns the information about the frame buffer structure including the assignment of each frame buffer bit to a color channel bit. It is recommended that graphics software uses this function in order to achieve a correct color representation.